1 : // Copyright 2012 Google Inc. All Rights Reserved.
2 : //
3 : // Licensed under the Apache License, Version 2.0 (the "License");
4 : // you may not use this file except in compliance with the License.
5 : // You may obtain a copy of the License at
6 : //
7 : // http://www.apache.org/licenses/LICENSE-2.0
8 : //
9 : // Unless required by applicable law or agreed to in writing, software
10 : // distributed under the License is distributed on an "AS IS" BASIS,
11 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 : // See the License for the specific language governing permissions and
13 : // limitations under the License.
14 : //
15 : // Utility functions for use with disassembler callbacks.
16 :
17 : #ifndef SYZYGY_CORE_DISASSEMBLER_UTIL_H_
18 : #define SYZYGY_CORE_DISASSEMBLER_UTIL_H_
19 :
20 : #include <string>
21 :
22 : #include "base/basictypes.h"
23 : #include "syzygy/assm/register.h"
24 : #include "distorm.h" // NOLINT
25 : #include "mnemonics.h" // NOLINT
26 :
27 m : namespace core {
28 :
29 m : using assm::Register;
30 m : using assm::RegisterId;
31 :
32 : // Wrapper for the distorm_decompose function to patch a bug in distorm.
33 : // @param ci Structure containing some information about the code to decompose
34 : // (code origin, code data, code length, decoding mode and features).
35 : // @param result Array of type _DecodeInst which will be used by this function
36 : // in order to return the disassembled instructions.
37 : // @param max_instructions The maximum number of entries in the result array
38 : // that you pass to this function, so it won't exceed its bound.
39 : // @param used_instructions_count Number of the instruction that successfully
40 : // were disassembled and written to the result array.
41 : // @returns DECRES_SUCCESS on success (no more to disassemble), DECRES_INPUTERR
42 : // on input error (null code buffer, invalid decoding mode, etc...),
43 : // DECRES_MEMORYERR when there are not enough entries to use in the result
44 : // array, BUT YOU STILL have to check for usedInstructionsCount!
45 m : _DecodeResult DistormDecompose(_CodeInfo* ci,
46 m : _DInst result[],
47 m : unsigned int max_instructions,
48 m : unsigned int* used_instructions_count);
49 :
50 : // Decodes exactly one instruction from the given buffer.
51 : // @param address the address of the instruction, as an absolute address
52 : // consistent with the image's base address. If this is not provided a
53 : // fake address of 0x10000000 will be used.
54 : // @param buffer the buffer containing the data to decode.
55 : // @param length the length of the buffer.
56 : // @returns true if an instruction was decoded, false otherwise.
57 m : bool DecodeOneInstruction(
58 m : uint32 address, const uint8* buffer, size_t length, _DInst* instruction);
59 m : bool DecodeOneInstruction(
60 m : const uint8* buffer, size_t length, _DInst* instruction);
61 :
62 : // Dump text representation of exactly one instruction to a std::string.
63 : // @param instruction the instruction to dump.
64 : // @param data points to the raw byte sequences.
65 : // @param code_length the size of the raw representation.
66 : // @param buffer receives the text representation.
67 : // @returns true if @p instruction was successfully dumped, false otherwise.
68 m : bool InstructionToString(const _DInst& instruction,
69 m : const uint8_t* data,
70 m : int code_length,
71 m : std::string* buffer);
72 :
73 : // Determines if the given instruction is a recognized no-op. We only recognize
74 : // those instructions that we see generated by the MSVS toolchain.
75 : // @param instruction the instruction to evaluate.
76 : // @returns true if @p instruction is a recognized no-op, false otherwise.
77 m : bool IsNop(const _DInst& instruction);
78 :
79 : // Determines if the given instruction is a CALL.
80 : // @param instruction the instruction to evaluate.
81 : // @returns true if @p instruction is a call, false otherwise.
82 m : bool IsCall(const _DInst& instruction);
83 :
84 : // Determines if the given instruction is a RET.
85 : // @param instruction the instruction to evaluate.
86 : // @returns true if @p instruction is a return, false otherwise.
87 m : bool IsReturn(const _DInst& instruction);
88 :
89 : // Determines if the given instruction is a SYS.
90 : // @param instruction the instruction to evaluate.
91 : // @returns true if @p instruction is a return, false otherwise.
92 m : bool IsSystemCall(const _DInst& instruction);
93 :
94 : // Determines if the given instruction is a conditional branch.
95 : // @param instruction the instruction to evaluate.
96 : // @returns true if @p instruction is a conditional branch, false otherwise.
97 m : bool IsConditionalBranch(const _DInst& instruction);
98 :
99 : // Determines if the given instruction is a unconditional branch.
100 : // @param instruction the instruction to evaluate.
101 : // @returns true if @p instruction is a unconditional branch, false otherwise.
102 m : bool IsUnconditionalBranch(const _DInst& instruction);
103 :
104 : // Determines if the given instruction is a branch or any kind
105 : // @param instruction the instruction to evaluate.
106 : // @returns true if @p instruction is a branch, false otherwise.
107 m : bool IsBranch(const _DInst& instruction);
108 :
109 : // Determines if the given instruction has a PC-relative operand at the
110 : // given operand index.
111 : // @param instruction the instruction to evaluate.
112 : // @param operand_index the operand index to evaluate.
113 : // @returns true if @p instruction has a PC-relative operand at the given index.
114 m : bool HasPcRelativeOperand(const _DInst& instruction, int operand_index);
115 :
116 : // Determines if the given instruction is a control-flow instruction.
117 : // @param instruction the instruction to evaluate.
118 : // @returns true if @p instruction is a control-flow instruction, false
119 : // otherwise.
120 m : bool IsControlFlow(const _DInst& instruction);
121 :
122 : // Determines if the given instruction is an implicit control-flow instruction.
123 : // @param instruction the instruction to evaluate.
124 : // @returns true if @p instruction is an implicit control-flow instruction
125 : // (we can't explicitly compute the target due to the addressing mode)
126 : // false otherwise.
127 m : bool IsImplicitControlFlow(const _DInst& instruction);
128 :
129 : // Determines if the given instruction is an interrupt instruction.
130 : // @param instruction the instruction to evaluate.
131 : // @returns true if @p instruction is an interrupt instruction, false otherwise.
132 m : bool IsInterrupt(const _DInst& instruction);
133 :
134 : // Determines if the given instruction is the debug interrupt instruction.
135 : // @param instruction the instruction to evaluate.
136 : // @returns true if @p instruction is the debug interrupt instruction, false
137 : // otherwise.
138 m : bool IsDebugInterrupt(const _DInst& instruction);
139 :
140 : // @name Distorm _RegisterType conversion.
141 : // @{
142 :
143 : // Converts from a register to a Distorm _RegisterType.
144 : // @param reg The register object whose type we wish to retrieve.
145 : // @returns the Distorm register type.
146 m : _RegisterType GetRegisterType(const Register& reg);
147 :
148 : // Converts from a register id to a Distorm _RegisterType.
149 : // @param reg_id The register id to to convert to a _RegisterType.
150 : // @returns the Distorm register type.
151 m : _RegisterType GetRegisterType(RegisterId reg_id);
152 :
153 : // Given a Distorm register type, converts to a RegisterId.
154 : // @param distorm_reg_type The Distorm register type to be converted.
155 : // @returns the id of the register.
156 m : RegisterId GetRegisterId(uint32 distorm_reg_type);
157 :
158 : // Given a Distorm register type, returns the associated register object.
159 : // @param distorm_reg_type The Distorm register type to be converted.
160 : // @returns a const reference to the register object.
161 m : const Register& GetRegister(uint32 distorm_reg_type);
162 :
163 : // @}
164 :
165 m : } // namespace core
166 :
167 : #endif // SYZYGY_CORE_DISASSEMBLER_UTIL_H_
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