1 : // Copyright 2012 Google Inc. All Rights Reserved.
2 : //
3 : // Licensed under the Apache License, Version 2.0 (the "License");
4 : // you may not use this file except in compliance with the License.
5 : // You may obtain a copy of the License at
6 : //
7 : // http://www.apache.org/licenses/LICENSE-2.0
8 : //
9 : // Unless required by applicable law or agreed to in writing, software
10 : // distributed under the License is distributed on an "AS IS" BASIS,
11 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 : // See the License for the specific language governing permissions and
13 : // limitations under the License.
14 : //
15 : // Utility functions for use with disassembler callbacks.
16 :
17 : #ifndef SYZYGY_CORE_DISASSEMBLER_UTIL_H_
18 : #define SYZYGY_CORE_DISASSEMBLER_UTIL_H_
19 :
20 : #include <string>
21 :
22 : #include "base/basictypes.h"
23 : #include "syzygy/core/register.h"
24 : #include "distorm.h" // NOLINT
25 : #include "mnemonics.h" // NOLINT
26 :
27 m : namespace core {
28 :
29 : // Wrapper for the distorm_decompose function to patch a bug in distorm. The
30 : // access size for I_FNSTCW and I_FLDCW dst operand is 0 instead of 16.
31 : // TODO(sebmarchand): Remove this code once this is fixed in distorm.
32 : // @param ci Structure containing some information about the code to decompose
33 : // (code origin, code data, code length, decoding mode and features).
34 : // @param result Array of type _DecodeInst which will be used by this function
35 : // in order to return the disassembled instructions.
36 : // @param max_instructions The maximum number of entries in the result array
37 : // that you pass to this function, so it won't exceed its bound.
38 : // @param used_instructions_count Number of the instruction that successfully
39 : // were disassembled and written to the result array.
40 : // @returns DECRES_SUCCESS on success (no more to disassemble), DECRES_INPUTERR
41 : // on input error (null code buffer, invalid decoding mode, etc...),
42 : // DECRES_MEMORYERR when there are not enough entries to use in the result
43 : // array, BUT YOU STILL have to check for usedInstructionsCount!
44 m : _DecodeResult DistormDecompose(_CodeInfo* ci,
45 m : _DInst result[],
46 m : unsigned int max_instructions,
47 m : unsigned int* used_instructions_count);
48 :
49 : // Decodes exactly one instruction from the given buffer.
50 : // @param address the address of the instruction, as an absolute address
51 : // consistent with the image's base address. If this is not provided a
52 : // fake address of 0x10000000 will be used.
53 : // @param buffer the buffer containing the data to decode.
54 : // @param length the length of the buffer.
55 : // @returns true if an instruction was decoded, false otherwise.
56 m : bool DecodeOneInstruction(
57 m : uint32 address, const uint8* buffer, size_t length, _DInst* instruction);
58 m : bool DecodeOneInstruction(
59 m : const uint8* buffer, size_t length, _DInst* instruction);
60 :
61 : // Dump text representation of exactly one instruction to a std::string.
62 : // @param instruction the instruction to dump.
63 : // @param data points to the raw byte sequences.
64 : // @param code_length the size of the raw representation.
65 : // @param buffer receives the text representation.
66 : // @returns true if @p instruction was successfully dumped, false otherwise.
67 m : bool InstructionToString(const _DInst& instruction,
68 m : const uint8_t* data,
69 m : int code_length,
70 m : std::string* buffer);
71 :
72 : // Determines if the given instruction is a recognized no-op. We only recognize
73 : // those instructions that we see generated by the MSVS toolchain.
74 : // @param instruction the instruction to evaluate.
75 : // @returns true if @p instruction is a recognized no-op, false otherwise.
76 m : bool IsNop(const _DInst& instruction);
77 :
78 : // Determines if the given instruction is a CALL.
79 : // @param instruction the instruction to evaluate.
80 : // @returns true if @p instruction is a call, false otherwise.
81 m : bool IsCall(const _DInst& instruction);
82 :
83 : // Determines if the given instruction is a RET.
84 : // @param instruction the instruction to evaluate.
85 : // @returns true if @p instruction is a return, false otherwise.
86 m : bool IsReturn(const _DInst& instruction);
87 :
88 : // Determines if the given instruction is a SYS.
89 : // @param instruction the instruction to evaluate.
90 : // @returns true if @p instruction is a return, false otherwise.
91 m : bool IsSystemCall(const _DInst& instruction);
92 :
93 : // Determines if the given instruction is a conditional branch.
94 : // @param instruction the instruction to evaluate.
95 : // @returns true if @p instruction is a conditional branch, false otherwise.
96 m : bool IsConditionalBranch(const _DInst& instruction);
97 :
98 : // Determines if the given instruction is a unconditional branch.
99 : // @param instruction the instruction to evaluate.
100 : // @returns true if @p instruction is a unconditional branch, false otherwise.
101 m : bool IsUnconditionalBranch(const _DInst& instruction);
102 :
103 : // Determines if the given instruction is a branch or any kind
104 : // @param instruction the instruction to evaluate.
105 : // @returns true if @p instruction is a branch, false otherwise.
106 m : bool IsBranch(const _DInst& instruction);
107 :
108 : // Determines if the given instruction has a PC-relative operand at the
109 : // given operand index.
110 : // @param instruction the instruction to evaluate.
111 : // @param operand_index the operand index to evaluate.
112 : // @returns true if @p instruction has a PC-relative operand at the given index.
113 m : bool HasPcRelativeOperand(const _DInst& instruction, int operand_index);
114 :
115 : // Determines if the given instruction is a control-flow instruction.
116 : // @param instruction the instruction to evaluate.
117 : // @returns true if @p instruction is a control-flow instruction, false
118 : // otherwise.
119 m : bool IsControlFlow(const _DInst& instruction);
120 :
121 : // Determines if the given instruction is an implicit control-flow instruction.
122 : // @param instruction the instruction to evaluate.
123 : // @returns true if @p instruction is an implicit control-flow instruction
124 : // (we can't explicitly compute the target due to the addressing mode)
125 : // false otherwise.
126 m : bool IsImplicitControlFlow(const _DInst& instruction);
127 :
128 : // Determines if the given instruction is an interrupt instruction.
129 : // @param instruction the instruction to evaluate.
130 : // @returns true if @p instruction is an interrupt instruction, false otherwise.
131 m : bool IsInterrupt(const _DInst& instruction);
132 :
133 : // Determines if the given instruction is the debug interrupt instruction.
134 : // @param instruction the instruction to evaluate.
135 : // @returns true if @p instruction is the debug interrupt instruction, false
136 : // otherwise.
137 m : bool IsDebugInterrupt(const _DInst& instruction);
138 :
139 : // @name Distorm _RegisterType conversion.
140 : // @{
141 :
142 : // Converts from a register to a Distorm _RegisterType.
143 : // @param reg The register object whose type we wish to retrieve.
144 : // @returns the Distorm register type.
145 m : _RegisterType GetRegisterType(const Register& reg);
146 :
147 : // Converts from a register id to a Distorm _RegisterType.
148 : // @param reg_id The register id to to convert to a _RegisterType.
149 : // @returns the Distorm register type.
150 m : _RegisterType GetRegisterType(RegisterId reg_id);
151 :
152 : // Given a Distorm register type, converts to a RegisterId.
153 : // @param distorm_reg_type The Distorm register type to be converted.
154 : // @returns the id of the register.
155 m : RegisterId GetRegisterId(uint32 distorm_reg_type);
156 :
157 : // Given a Distorm register type, returns the associated register object.
158 : // @param distorm_reg_type The Distorm register type to be converted.
159 : // @returns a const reference to the register object.
160 m : const Register& GetRegister(uint32 distorm_reg_type);
161 :
162 : // @}
163 :
164 m : } // namespace core
165 :
166 : #endif // SYZYGY_CORE_DISASSEMBLER_UTIL_H_
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